1. Field of the Invention
The present application relates to an array substrate for a display device, and more particularly, to an array substrate that includes a thin film transistor having a high mobility due to prevention of a surface damage by a dry etching process and a method of fabricating the array substrate.
2. Discussion of the Related Art
As information age progresses, display devices processing and displaying an amount of information have been developed. Among the various types of display devices, liquid crystal display (LCD) devices or electroluminescent display (ELD) devices having light weight, thin profile, and low power consumption have been substituted for cathode ray tube (CRT) devices.
Among LCD devices, active matrix LCD (AM-LCD) devices that employ switching elements and pixel electrodes arranged in a matrix structure are the subject of significant research and development because of their high resolution and superior suitability for displaying moving images.
In addition, since organic electroluminescent display (OELD) devices, which is referred to as organic light emitting diode (OLED) devices, have an emissive type with high brightness and low driving voltage, the OLED devices have advantages such as high contrast ratio, ultra thin profile, short response time of about several microseconds, wide viewing angle and stability at low temperature. For example, the OLED devices may be driven with a driving voltage of about 5V DC to about 15V DC. Accordingly, design and fabrication of a driving circuit for the OLED devices are simplified.
Each of the LCD device and the OLED device includes an array substrate having a thin film transistor as a switching element for a pixel region.
FIG. 1 is a cross-sectional view showing an array substrate for a display device according to the related art.
In FIG. 1, a gate line (not shown) and a gate electrode 15 are formed in a pixel region P on a substrate 11, and a gate insulating layer 18 is formed on the gate line and the gate electrode 15. A semiconductor layer 28 including an active layer 22 of intrinsic amorphous silicon and an ohmic contact layer 26 of impurity-doped amorphous silicon is formed on the gate insulating layer 18 over the gate electrode 15. Source and drain electrodes 36 and 38 spaced apart from each other are formed on the ohmic contact layer 26. The gate electrode 15, the gate insulating layer 18, the semiconductor layer 28, the source electrode 36 and the drain electrode 38 constitute a thin film transistor (TFT) Tr.
In addition, a passivation layer 42 is formed on the TFT Tr. The passivation layer 42 has a drain contact hole 45 exposing the drain electrode 38. A pixel electrode 50 is formed on the passivation layer 42 in the pixel region P. The pixel electrode 50 is connected to the drain electrode 38 through the drain contact hole 45.
A data line 33 including first and second patterns 27 and 23 is formed on the substrate 11. The data line 33 crosses the gate line to define the pixel region P. The first and second patterns 27 and 23 have the same layers as the ohmic contact layer 26 and the active layer 22, respectively.
The active layer 22 of the semiconductor layer 28 has a first portion exposed through the ohmic contact layer 26 and a second portion under the ohmic contact layer 26. The first and second portions of the active layer 22 have first and second thicknesses t1 and t2, respectively, different from each other. (t1≠t2) The thickness difference of the active layer 22 that results from a fabrication method causes degradation in characteristic of the TFT Tr.
FIGS. 2A to 2E are cross-sectional views showing a process of forming a semiconductor layer, a source electrode and a drain electrode of an array substrate for a display device according to the related art. For simplicity in illustration, a gate electrode and a gate insulating layer between the array substrate and the semiconductor layer are omitted in FIGS. 2A to 2E.
In FIG. 2A, an intrinsic amorphous silicon layer 20, an impurity-doped silicon layer 24 and a metal layer 30 are sequentially formed on the substrate 11. After a photo resist (PR) layer (not shown) is formed on the metal layer 30, a light is irradiated onto the PR layer using a photo mask to form a first PR pattern 91 corresponding to the source and drain electrodes and a second PR pattern 92 corresponding to the first portion exposed through the source and drain electrodes 36 and 38 (of FIG. 1). The first and second PR patterns 91 and 92 have third and fourth thicknesses t3 and t4, respectively. The fourth thickness t4 is smaller than the third thickness t3. (t4<t3)
In FIG. 2B, the metal layer 30 (of FIG. 2A), the impurity-doped silicon layer 24 (of FIG. 2A) and the intrinsic amorphous silicon layer 20 (of FIG. 2A) are etched using the first and second PR patterns 91 and 92 as an etching mask so that a source-drain pattern 31, an impurity-doped amorphous silicon pattern 25 and the active layer 22 can be formed.
In FIG. 2C, through an ashing process, the second PR pattern 92 (of FIG. 2A) having the fourth thickness t4 (of FIG. 2A) is removed and the first PR pattern 91 (of FIG. 2A) having the third thickness t3 (of FIG. 2A) is partially removed so that a third PR pattern 93 having a reduced thickness can be formed on the source-drain pattern 31.
In FIG. 2D, the source-drain pattern 31 (of FIG. 2C) is etched using the third PR pattern 93 as an etching mask so that the source and drain electrodes 36 and 38 can be formed and the impurity-doped amorphous silicon pattern 25 can be exposed between the source and drain electrodes 36 and 38.
In FIG. 2E, the impurity-doped amorphous silicon pattern 25 (of FIG. 2D) exposed between the source and drain electrodes 36 and 38 is etched through a dry etching step so that the ohmic contact layer 26 can be formed under the source and drain electrodes 36 and 38. When the dry etching step is performed for an insufficient time, the impurity-doped amorphous silicon pattern 25 may remain on the active layer 22 between the source and drain electrodes 36 and 38. The remaining impurity-doped amorphous silicon pattern may connect the source and drain electrodes 36 and 38 to deteriorate the TFT Tr (of FIG. 1). For the purpose of removing the impurity-doped amorphous silicon pattern 25 exposed between the source and drain electrodes 36 and 38 completely, the dry etching step is performed for a sufficiently long time. Accordingly, the active layer 22 under the impurity-doped amorphous silicon pattern 25 exposed between the source and drain electrodes 36 and 38 is partially etched.
As a result, the first portion of the active layer 22 exposed through the ohmic contact layer 26 has the first thickness t1 and the second portion of the active layer 22 under the ohmic contact layer 26 has the second thickness t2 different from the first thickness t1. (t1≠t2) The thickness difference of the active layer 22 causes degradation in characteristic of the TFT Tr (of FIG. 1). In addition, since the active layer 22 is partially removed during the drying etching step for the ohmic contact layer 26, the intrinsic amorphous silicon layer 20 (of FIG. 2A) is formed to have a sufficient thickness, for example, within a range of about 1500 Å to about 1800 Å. Accordingly, the deposition time for the intrinsic amorphous silicon layer 20 (of FIG. 2A) increases and the productivity is reduced.
The TFT connected to the gate line and the data line transmits the data signal to the pixel electrode periodically. Since amorphous silicon is disordered, the amorphous silicon has a quasi-stable state when a light is irradiated or when an electric field is applied. Accordingly, the TFT including the active layer of amorphous silicon has a disadvantage in stability. Further, since the carrier mobility is within a range of about 0.1 cm2/V·s to about 1.0 cm2/V·s in the channel region, the TFT including the active layer of amorphous silicon can not be used as a switching element for a driving circuit.
To solve the above problems, the TFT including the active layer of poly crystalline silicon has been suggested. The polycrystalline silicon may be formed through a crystallization process for amorphous silicon using a laser apparatus.
FIG. 3 is a cross-sectional view showing an array substrate having a thin film transistor according to the related art.
In FIG. 3, a thin film transistor (TFT) Tr including a semiconductor layer 55 of polycrystalline silicon is formed on a substrate 51. The semiconductor layer 55 includes an active region 55a and source and drain regions 55b at both sides of the active region 55a. Although the active region 55a includes intrinsic polycrystalline silicon, the source and drain regions 55b include impurity-doped polycrystalline silicon. The source and drain regions 55b include negative impurities of high concentration (n+) or positive impurities of high concentration (p+). Accordingly, a doping step is required for the source and drain regions 55b and an implantation apparatus is additionally required for the doping step. As a result, fabrication cost increases. Furthermore, a new fabrication line of the array substrate is required for the implantation apparatus.